The present invention relates to an accumulator for use in updating coefficients, and more particularly to a two stage accumulator for updating the coefficients of an adaptive equalizer or the like.
Digital data, for example digitized video for use in broadcasting high definition television (HDTV) signals, can be transmitted over terrestrial very high frequency (VHF) or ultra high frequency (UHF) analog channels for communication to end users. Analog channels deliver corrupted and transformed versions of their input waveforms. Corruption of the waveform, usually statistical, may be additive and/or multiplicative, because of possible background thermal noise, impulse noise, and fades. Transformations performed by the channel are frequency translation, nonlinear or harmonic distortion, and time dispersion.
In order to communicate digital data via an analog channel, the data is modulated using, for example, a form of pulse amplitude modulation (PAM). Typically, quadrature amplitude modulation (QAM) is used to increase the amount of data that can be transmitted within an available channel bandwidth. QAM is a form of PAM in which a plurality, such as sixteen or thirty-two, bits of information are transmitted together in a pattern referred to as a "constellation".
In pulse amplitude modulation, each signal is a pulse whose amplitude level is determined by a transmitted symbol. In 16-QAM, symbol amplitudes of -3, -1, 1 and 3 in each quadrature channel are typically used. In bandwidth efficient digital communication systems, the effect of each symbol transmitted over a time-dispersive channel extends beyond the time interval used to represent that symbol. The distortion caused by the resulting overlap of received symbols is called intersymbol interference (ISI). This distortion has been one of the major obstacles to reliable high speed data transmission over low background noise channels of limited bandwidth. A device known as an "equalizer" is used to deal with the ISI problem.
In order to reduce the intersymbol interference introduced by a communication channel, rather precise equalization is required. Furthermore, the channel characteristics are typically not known beforehand. Thus, it is common to design and use a compromise (or a statistical) equalizer that compensates for the average of the range of expected channel amplitude and delay characteristics. A least mean square (LMS) error adaptive filtering scheme has been in common use as an adaptive equalization algorithm for many years. This algorithm is described in B. Widrow and M. E. Hoff, Jr., "Adaptive Switching Circuits" in IRE Wescon Conv. Rec., Part 4, pp. 96-104, Aug. 1960. The use of the LMS algorithm in an adaptive equalizer to reduce intersymbol interference is discussed in S. U. H. Qureshi, "Adaptive Equalization", Proc. IEEE, Vol. 73, No. 9, pp. 1349-1387, September 1987.
Commonly assigned, copending U.S. patent application Ser. No. 07/733,791 filed on Jul. 26, 1991 discloses a method and apparatus for updating coefficients in a complex adaptive equalizer. Specifically, convergence of a complex adaptive equalizer used in digital communications is substantially improved by updating all coefficients of the equalizer during each filter clock cycle. A plurality of successive delay stages are coupled to provide a plurality of sets of delayed signal data from an input signal. Each set of delayed data is multiplied by an error signal to provide a plurality of products. Each product is concurrently updated with previous product data to provide a plurality of sets of updated coefficients. The updated coefficient sets are selectively input to an equalizer filter stage.
In a specific embodiment illustrated in the aforementioned copending patent application, a plurality of parallel processing paths are used, each to update one of the products. Each of the parallel processing paths includes an adder having a first input for receiving one of the plurality of products, a second input and an output. A delay circuit is coupled to receive product data from the adder output and to feed delayed product data back to the second adder input. The parallel processing paths can further include means for truncating and/or adjusting the gain of the updated coefficients output from the adder. Sets of updated coefficients from the various parallel paths are multiplexed to provide a clocked stream of coefficient sets for input to the equalizer filter stage.
A disadvantage to using adders as accumulators in the implementation disclosed in the aforementioned copending patent application is that such devices require an inordinate amount of space in a very large scale integration (VLSI) integrated circuit. Thus, the use of a conventional adder and delay stage as an accumulator increases the cost and may decrease the performance of an adaptive equalizer implementation.
It would be advantageous to provide an improved implementation for an accumulator that can be used in connection with an adaptive equalizer or the like. Such an implementation should avoid the need for a long bit adder which requires substantial hardware and may slow down the equalizer processing speed. It would be further advantageous to provide such an accumulator implementation which will improve the convergence of the coefficients by dynamically maintaining limits on the coefficient magnitudes.
The present invention provides a two stage accumulator enjoying the aforementioned advantages.